A Literature Survey on Low PDP Adder Circuits
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چکیده
In this paper, the various low power full adder circuits with high speed operation have been analyzed. The adder is the basic building blocks of arithmetic circuits, so a small amount of power or delay reduction leads to greatest power saving or better performance of the circuit. Various design techniques are available for low power high speed full adders. All the adders are simulated using tanner EDA tools with 45nm technology. The power consumption and delay of various adders have been computed and analyzed. Also power delay product and number of transistors for each design has been calculated and compared with other design. These performance results will help the circuit designer to choose right adder for their required application.
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